Column 8: If one CPU is not enough. (2011-08-17)

It has always been much easier to build two of the same CPUs than a single CPU that runs twice as fast. If you purchase a machine with the fastest CPU available (at any given time). buying a CPU that runs twice as fast is simply not possible. Buying more of the same CPUs is indeed possible (if expensive) and building a machine that can use them all is also possible. Symmetric Multiprocessing (SMP) machines contain more than one CPU, but are otherwise a single system with a single main memory and a single I/O bus.

These days, multi-core CPUs are the standard and it would be foolish if Coreboot could not support them. Coreboot must configure the hardware on an SMP system correctly, it must provide the correct tables to the Operating System (so it knows which CPUs it should enable) and in most cases it has to run some initialization code on each CPU.

There are several types of SMP.

Different types of SMP can be combined in a single system. A top-of the line motherboard could have two physical CPUs (classic SMP), each having four cores (multi-core), each being capably of Hyperthreading.


SMP systems were already common in the mainframe world in the 1970s. In the 1980s Sequent built SMP machines (running Unix) based on off-the-shelf microcomputers. In 1987 they introduced a model based on the Intel 80386. They pioneered many of the hardware and software principles found in modern SMP machines running Linux.

With the introduction of the Intel Pentium in 1993, SMP on PC-class machines began for real. No mainstream operating system supported SMP at that time. Windows NT4.0 (1995) and Linux 2.0 (1996) had some support for SMP. Until 2003, SMP was reserved for high-end motherboards and high-end CPUs. When Intel introduced its Pentium 4 with Hyperthreading, SMP-capable systems started to be common in home computers. In 2006, dual-core CPUs had become common. As of 2011, essentially all PC-class machines have at least a dual-core CPU.


The hardware of an SMP system is very complex. It involves (among other things) the following:

In a multi-core CPU these tasks are performed on-chip/

SMP systems use the APIC (Advanced Programmable Interrupt Controller) logic to deliver interrupts to one or more CPUs. This logic is now part of the CPU. Device interrupts can be delivered to one or more CPUs and CPUs can send interrupts among themselves (Inter Processor Interrupt or IPI). In particular the boot CPU can start and stop the other CPUs in the system via a sequence of IPIs.

When a hardware reset occurs, one CPU starts actually running and the others are stopped. The CPU that starts running is the boot CPU, the others are called Application Processors. In an x86 SMP system, each application processor starts in real mode at a page-aligned address (multiple of 4096), which has to lie in the real mode address range. The boot CPU has to send a sequence of IPIs (with the start address as a parameter) to start each application processor.

BIOS and the Operating System

In short, the responsibilities of the BIOS and the Operating System are as follows: the BIOS has to supply the correct tables that specify which CPUs are available, the Operating System has to start them up.

Nearly all of Coreboot is run by the boot CPU. Coreboot has to perform the following tasks for SMP systems:

The operating system has the following tasks to start the application processors up:

Setting up NUMA

The AMD Opteron CPUs have their own integrated memory controllers and they have SMP capability, resulting in a NUMA system. The job of setting this up is a bit tougher than for most other systems. The main issue is that each CPU has to run its own RAM initialization code. In a system with many CPUs, the boot CPU may not be able to set up all HyperTransport links, so this has to be delegated to application processors as well. A few notes: